1. Field of the Invention
This invention relates to an A/D converter, and more particularly, to an A/D converter which operates in high speed by adjusting a duty ratio of a sampling clock and a duty control method of a sampling clock.
2. Description of the Related Art
An A/D converter converts an analog signal to a digital signal. In the A/D converter, an analog input signal is sampled and held in a sample and hold circuit. The analog input signal, which is output from the sample and hold circuit, is converted to a digital signal by an A/D converting circuit. In the A/D converter, a sampling clock is applied to the sample and hold circuit. For example, a sampling period corresponds to “H” level of the sampling clock, and a holding period corresponds to “L” level of the sampling clock. The sample and hold circuit samples the analog input signal during the sampling period, and a sampling capacitor in the sample and hold circuit is charged according to the analog input signal. On the other hand, the sample and hold circuit holds and outputs the sampled analog input signal during the holding period.
When the holding period is changed to the sampling period, there is a time period to charge the sampling capacitor to a voltage which is equal to the analog input signal.
When the sampling period is changed to the holding period, there is a time period to settle an output voltage because of a transient response.
The time period to charge the sampling capacitor to the voltage which is equal to the analog input signal is called an acquisition time. The time period to settle the output voltage is called a settling time.
A duty ratio of the sampling clock is 50% in a conventional A/D converter. That is, the sampling period and the holding period have the same length of time in a conventional A/D converter. Therefore, the minimum period of the sampling clock is determined based on a longer period of the sampling period or the holding period. The minimum period Tmin of the sampling clock is twice longer than the longer period of the sampling period or the holding period.
The acquisition time and the settling time are generally different. Therefore, when the acquisition time is 2.5 nsec and the settling time is 5 nsec, the minimum period of the sampling clock becomes 2*5=10 nsec. This period of the sampling clock corresponds to 100 Mega-Samples/sec (hereinafter, MS/sec). Thereby, it is difficult to achieve a high speed operation of the A/D converter.
On the other hand, Japanese Unexamined Patent Application Publication No. 5-244001 discloses a sampling clock which has a duty ratio different from 50%. In Japanese Unexamined Patent Application Publication No. 5-244001, the duty ratio of the sampling clock is uniformly changed from 50%. Therefore, the duty ratio of the sampling clock can not be adjusted based on environments.
As described above, the duty ratio of the sampling clock is not set based on environments. Therefore, it is difficult for the A/D converter to perform a high speed operation based on environments.